This invention relates to Drain Extended MOS transistors.
Scaling of CMOS technology leads to not only an increase in device density but also reduction in gate-oxide thickness and hence a reduction in transistor supply voltages. However, chip supply voltages have not decreased in line with the reduction in transistor supply voltages.
Drain-Extended MOS (DE-MOS) transistors have been designed to allow increased drain voltages, but there is no change in the voltage tolerable at the gate of the device. The restricted gate voltage typically leads to the use of gate drive circuits, but such circuits greatly increase the circuit area as the gate drive circuit can be as big as the DE-MOS transistor.
Another approach is to utilise dedicated high-voltage transistors, for example by the addition of a further gate-oxide to a conventional dual gate-oxide process. However, such systems increase the manufacturing cost and cycle time and are therefore undesirable.
There is therefore a requirement for a CMOS technology providing an increased transistor gate supply voltage. The embodiments described below are not limited to implementations which solve any or all of the disadvantages discussed above.